An AI chip spec sheet is full of huge numbers, and most of them come with conditions in the small print. What each number means, why the same chip shows figures that differ a hundredfold, which footnotes halve them, and a checklist to use on any claim. Start simple, go as deep as you like.
Stuck at any point? Ask an AI about this page →The biggest number on an NVIDIA spec table usually has a small asterisk. It means the figure assumes "sparsity", a trick where the chip skips half the numbers in a model. NVIDIA's own footnote says: "Specification in Sparse. Dense is 1/2 sparse spec shown" 1.
So the first rule is simple: if the row has an asterisk, halve it.
On the H100 page, the asterisk sits on the TF32, BFLOAT16, FP16, FP8 and INT8 rows, but not on FP64 or FP32 2. NVIDIA's DGX B200 page spells the same thing out: "Specification shown in sparse. Dense performance is 1/2 sparse spec shown", and prints both, as in "144 PFLOPS | 72 PFLOPS" 3.
AMD handles it differently, listing sparsity as its own row: MI355X shows FP16 "Matrix: 2.5 PFLOPs" and "Matrix with Sparsity: 5 PFLOPs" 4. Both companies also note that these are calculated peaks, not measurements: AMD's footnote says the figures are "Based on calculations by AMD Performance Labs" 5.
One chip has many speeds, because it can work with numbers of different sizes. Smaller numbers mean more sums per second. The same H100 is rated at 34 teraflops for 64-bit maths and 3,958 teraflops for 8-bit maths with sparsity: a 116-fold spread on one chip 2.
So a speed with no precision attached is not a number at all.
Two wrinkles worth knowing. On Hopper, BF16 and FP16 are the same speed, so BF16 buys range rather than throughput 2. And inference-focused parts drop the rows they no longer need: an 8-GPU HGX B200 lists 296 TFLOPS of FP64, while HGX B300 lists 10 1. Peak is also not delivered: measured "model FLOPs utilization" on large training runs ran from 21.3% for GPT-3 to 46.2% for PaLM 6.
Two units appear. FLOPS counts floating-point sums; TOPS or POPS counts whole-number (integer) sums 1 4. Phone and laptop chips are usually quoted in TOPS, which is not comparable with a data-centre FLOPS figure.
The format names matter too: FP16, BF16, FP8 and FP4 are different ways of writing a number in 16, 8 or 4 bits 7.
"FP4" is the trap. NVIDIA's NVFP4 groups 16 values sharing an 8-bit FP8 scale, plus a second scale for the whole tensor; the open MX standard's MXFP4 groups 32 values sharing a power-of-two scale 11 12. Both are 4-bit at the element level, so two chips can quote "FP4 petaflops" and mean different things. NVIDIA reports NVFP4 losing "1% or less" accuracy against FP8 on one model 11. See How AI chips work for why smaller numbers are faster.
Two memory numbers matter, and they answer different questions. Capacity (in gigabytes) decides whether a model fits. Bandwidth (in terabytes a second) decides how fast answers come out 2 13.
The clearest proof that bandwidth matters is NVIDIA's own: the H200 has exactly the same peak compute as the H100, 3,958 teraflops of FP8, but 141 GB at 4.8 TB/s instead of 80 GB at 3.35 TB/s 2 13. NVIDIA reports up to 28% more throughput on a 70-billion-parameter model at the same 700 watts, crediting memory: it says the extra bandwidth relieves "bottlenecks in memory bandwidth-bound portions of the workload" 14.
Capacity and bandwidth do not move together: B200 and B300 both have 8 TB/s, but 192 GB and 288 GB 15. Watch the unit as well: a DGX B200's "1,440 GB total" is eight GPUs, 180 GB each 3. Today's chips use HBM3 or HBM3E; the HBM4 standard, published in April 2025, allows up to 2 TB/s per stack 16. Our AI memory guide covers that supply.
Ask what the number counts. Modern figures come per chip, per server of eight, or per rack of 72 15 3 17:
"One chip" is itself slippery: a Blackwell GPU is "two reticle-limited dies connected by a 10 terabytes per second chip-to-chip interconnect" working as "a unified single GPU" 18, and one Google Ironwood chip holds two compute cores across two chiplets 19. Google labels its rows per chip or per pod, which makes them easy to read 19 20.
Link speeds are usually the two directions added together: NVIDIA describes its sixth-generation NVLink as "3 TB/s bidirectional" per GPU 21 22, and Google's table is headed "Bidirectional inter-chip interconnect (ICI) bandwidth" at 1,200 GB/s per chip 19. Halve for one direction. Watch bits against bytes too: Google's blog gives the same link as 9.6 Tb/s, which is the same as 1,200 GB/s 23 19.
Power figures are design targets, not measurements, and they are often adjustable. NVIDIA lists the H100 at "Up to 700W (configurable)" 2. A whole DGX B200 server draws about 14.3 kW 3, and a 72-GPU rack about 120 kW 24.
The setting changes the product. NVIDIA reports its H200 delivering 28% more throughput than H100 at 700 W, and 43 to 45% more at 1,000 W 14. Cooling decides density too: AMD says a rack holds "up to 64 GPUs" with air cooling and "up to 128 GPUs" with direct liquid cooling 5.
Per-GPU power does not add up to server power: eight roughly 1,000-watt GPUs sit in a 14.3 kW server once processors, networking and losses are counted 3. NVIDIA contrasts today's racks with data centres that "once operated at 20 kW per rack" 24. Efficiency claims in the same posts are the vendor's own 24.
A spec sheet says what a chip could do in theory. Benchmarks say what a system did. The main shared benchmark is MLPerf, run by MLCommons, which "measures how fast systems can process inputs and produce results using a trained model" 25.
MLPerf has two divisions: the closed division "requires using the same model as the reference implementation", which is what makes results comparable; the open division "allows using a different model or retraining" 25. Each entry is also marked Available, Preview, or Research/Development/Internal, so you can tell whether you could actually buy the system 25 26. Training results are wall-clock times to reach a set quality, with run-to-run variation of roughly 2.5 to 5% 27.
The caution is that MLPerf results are submitted by vendors, on their own systems and software; MLCommons standardises the model, data, load pattern and accuracy target, not the tuning 26. Third-party services such as Artificial Analysis measure something different again, describing what a served endpoint delivers, tested "8 times per day" from one cloud region, with time-to-first-token "sensitive to server location" 28. That measures a provider's deployment, not a chip.
Ten questions to ask of any chip claim:
Two habits help. First, read the footnote that names the test: Apple's states "Testing was conducted by Apple in February 2026 using preproduction 16-inch MacBook Pro systems" 29. Second, notice what is missing: Apple published 38 trillion operations a second for M4 and has not published such a figure since 30 29. Our brand guides quote the vendors' own figures with these caveats attached; start at the AI Chips hub.
30 sources, all checked September 2026. Official = the company or organisation’s own page; Filing = a document filed with a regulator or an annual report; Standard = a published industry standard; Paper = a peer-reviewed or conference paper; Research = an independent research body; Government = a government page; Press = news coverage, used only where no official source exists.
Newest stories mentioning How to Read a Chip Spec Sheet, straight from the companies’ own newsrooms and the wider press. Links open the original.
Opens your assistant with this page as the source, and a question rather than a summary. It will ask what you are building before it answers.
Nothing is sent from here. The link carries only this page’s title and address.