Every step from a handful of sand to a working AI rack: purifying silicon, growing crystals, printing patterns with light, stacking memory, packaging, testing and building the rack. Who does each step, where, and what it costs.
Stuck at any point? Ask an AI about this page →Every chip starts as sand. Silicon is about a quarter of the Earth's crust by weight, second only to oxygen 1. But chip silicon must be astonishingly pure: electronic-grade silicon may contain only one foreign atom per billion silicon atoms 1.
First, quartz is turned into metallurgical-grade silicon that is 98–99% pure. That is converted into a liquid chemical (trichlorosilane), distilled, and deposited back onto thin silicon rods at over 1,000 °C in what is called the Siemens process 2. The rods are crushed into chunks, cleaned in acid and ultrapure water, and packed in cleanrooms for wafer makers 2.
Purity is quoted in "nines". Tokuyama describes semiconductor-grade polysilicon as 99.999999999% pure (eleven nines) 3; Wacker specifies twelve nines for semiconductor use 2; SUMCO says metal impurities are held to no more than a few parts per billion 4. Intel's older educational kit quotes 99.9999999% for the finished crystal 1. The figures differ because they measure different stages and impurities; all are far beyond almost any other manufactured material.
The pure silicon is melted and a single perfect crystal is slowly pulled out of the melt, like drawing a candle from wax. That crystal, called an ingot, is sliced into thin discs called wafers. Today's chips are made on wafers 300 mm (about 12 inches) across 1.
The method is called Czochralski growth: polysilicon is melted at about 1,420 °C in a crucible, a small seed crystal is dipped in and slowly rotated and pulled upward, and the silicon freezes onto it in one continuous crystal 4. Intel's older kit put a finished ingot at about 100 kg 1.
Turning an ingot into a usable wafer takes several more steps: slicing into roughly 1 mm slices with a wire or diamond saw, lapping flat with an abrasive, chemically etching away the damage, mirror-polishing, then cleaning and inspection 5. Wafer flatness matters because later steps print features only nanometres wide across the whole surface.
Chips are made in cleanrooms, because a single speck of dust can ruin a chip. Intel says the air in its fab cleanrooms has 1,000 times fewer particles than a hospital operating room 6. Workers wear full "bunny suits", and even paper and pencils are banned because they shed dust 6.
Cleanrooms are graded by how many particles are allowed. The international standard, ISO 14644-1, runs from ISO Class 1, allowing at most 10 particles of 0.1 micrometre or larger per cubic metre, to ISO 9 7. Air flows from ceiling to floor through filters to sweep particles away 8.
Modern fabs keep wafers away from people altogether. Wafers travel in sealed pods (FOUPs) carried by robot vehicles running on ceiling rails 8, so the cleanest air only needs to be inside the pods and machines. Intel said in 2018 that its D1X fab in Oregon covered roughly four football fields 6.
A chip's circuits are printed onto the wafer with light, like a photographic negative. The most advanced machines use extreme ultraviolet (EUV) light with a wavelength of just 13.5 nanometres 9. Only one company in the world makes EUV machines: ASML, in the Netherlands 10.
EUV light is made by firing lasers at tiny droplets of molten tin, about 25 micrometres across, travelling at 70 metres per second. Each droplet is hit twice, first to flatten it and then to vaporise it into a glowing plasma that emits EUV light, and this happens 50,000 times a second 9. ASML says its NXE:3800E machine reached 220 wafers an hour in its own factory tests 11.
Intel described an EUV machine in 2021 as weighing nearly 200 tonnes with about 100,000 parts, shipped in 40 freight containers on 20 trucks and three Boeing 747 cargo planes 12.
The next step is High-NA EUV. It raises the lens system's numerical aperture from 0.33 to 0.55, letting it print finer features; ASML's EXE:5000 has 8 nm resolution and can print more than 185 wafers an hour 13. ASML says its EXE:5200B is designed for volume production of chips beyond 2 nm 14, and that by the end of 2025 customers had run more than 400,000 wafers on High-NA machines 10.
A chip is built up layer by layer, like a tiny city with many floors. Each layer goes through the same cycle: coat, print with light, etch away, add material, flatten. The US chip industry association says wafer making can take up to 1,400 steps 15, and ASML says modern chips can have up to 100 layers that must line up to within nanometres 16.
ASML lists the core steps as depositing thin films, coating with light-sensitive resist, exposing through a patterned mask, etching, and ion implantation, which fires charged atoms into the silicon to change how it conducts electricity 17. Between layers, chemical-mechanical planarization presses the wafer against a spinning pad to leave a perfectly flat surface for the next layer 18. IBM Research notes that about a dozen process types are each repeated 40 to 100 times, which is how a chip reaches 1,000 or more steps 19.
Time is the hidden constraint. The Semiconductor Industry Association says wafer fabrication takes about 12 weeks on average and 14 to 20 weeks for advanced processes, and a finished chip can take up to 26 weeks including about 6 weeks of assembly, test and packaging 15. Defects can arise months before a wafer's final measurement, which is why inspection happens throughout the line, not just at the end 19 20.
You will hear chips described as "3 nanometre" or "2 nanometre". Those names are labels for a generation of manufacturing, not a measurement of anything on the chip. Intel says the names stopped matching real transistor sizes in 1997 21.
TSMC started volume production of its 2 nm process (N2) in the last quarter of 2025, using a new "nanosheet" transistor design 22. Its next steps, N2P and A16 (which adds power wiring on the back of the chip), are scheduled for volume production in the second half of 2026 23. TSMC was first to put 3 nm into volume production, in 2022 24.
How fast the industry moves to new nodes shows in TSMC's revenue: processes of 7 nm and below were 74% of its wafer revenue in 2025, up from 69% in 2024 23. In the second quarter of 2026, 3 nm was 30% of wafer revenue, 5 nm 33% and 2 nm already 3% 25. IEEE Spectrum has argued for replacing node names with density measures because the critical features of a "7 nm" transistor are considerably larger than 7 nm 26.
A finished wafer holds hundreds of chips. Each one is tested while still on the wafer, then the wafer is cut apart. Only the good chips (the industry calls them "known good dies") go on to be packaged, so money is not wasted packaging bad ones 27.
For AI chips, packaging is a big deal: the processor and its memory stacks are mounted side by side on a shared base, so they can talk very fast. TSMC's version of this is called CoWoS 28.
Wafers can be cut with a laser focused inside the silicon, which weakens it along a line so a stretching tape can then split the chips apart cleanly 29. After packaging, chips are tested again, and can be run hot under load ("burn-in") to catch early failures 30.
TSMC's CoWoS comes in three types: CoWoS-S with a silicon base up to 3.3 times the size a lithography machine can print in one exposure; CoWoS-R with a base made of wiring layers; and CoWoS-L, which mixes the two and was in volume production at 3.5 times that size from 2024 28. TSMC certified a 5.5-times version in 2025, with volume production starting in 2026 31.
Packaging has become a bottleneck in its own right. In July 2024 TSMC's CEO said CoWoS supply would stay very tight probably through 2025, and that capacity would more than double again from 2024 to 2025 32. By October 2025 TSMC said advanced packaging was slightly over 10% of its revenue and capacity was still very tight 33. Its largest packaging plant, Advanced Backend Fab 6 in Zhunan, opened in June 2023 and handles over a million 12-inch wafer equivalents of 3D packaging a year 34. All five of the packaging fabs TSMC lists are in Taiwan 35; it has announced two in Arizona 33.
The next level is stacking chips directly on top of each other. TSMC's SoIC joins chips with connections spaced less than 10 micrometres apart, and its 3 nm chip stacking entered volume production in 2025 36.
AI memory (HBM) is made by stacking memory chips on top of each other, 8, 12 or even 16 high, and drilling thousands of tiny vertical holes through them so signals can pass straight up and down 37 38. If just one chip in a stack is faulty, the whole stack can be lost, so every layer is tested first 27.
Those vertical connections are called through-silicon vias (TSVs). SK hynix fills the gaps between layers with a liquid that is then hardened, a method it calls MR-MUF 39. The newest HBM4 has 2,048 connections per stack, twice the previous generation 39. Samsung began shipping HBM4 in February 2026 at up to 3.3 TB/s per stack 40; Micron announced high-volume production of 12-high 36 GB HBM4 for NVIDIA's Vera Rubin in March 2026 41; SK hynix began mass shipments in the second quarter of 2026 42.
The next packaging method is hybrid bonding, which joins stacked chips copper-to-copper with no solder bumps, at spacings below 1 micrometre against about 20 for today's micro-bumps. SK hynix says full-scale hybrid bonding for HBM is most likely at HBM4E or HBM5, and that stack height rises from 720 to 775 micrometres under HBM4 37.
Demand outruns supply. SK hynix said in October 2025 that it had agreed HBM supply with key customers for 2026 and that its entire 2026 DRAM and NAND output was spoken for 43, and in July 2026 that customer demand exceeds its supply capability, with long-term agreements with about 10 customers 42.
The packaged chips are mounted on boards, the boards go into trays, and the trays go into a rack. NVIDIA's GB200 NVL72 rack holds 18 compute trays, each with 4 GPUs and 2 processors, plus 9 trays of switches that link all 72 GPUs together 44. The whole rack draws about 120 kilowatts and is cooled by liquid flowing through metal plates on each chip 44.
Racks are assembled by contract manufacturers. Foxconn said in August 2026 that it expected its AI rack shipments to more than double in 2026, with Vera Rubin racks entering mass production in the third quarter 45; Wistron opened a plant in Fort Worth, Texas, in July 2026 to build NVIDIA systems 46. NVIDIA's MGX reference design lets system makers build more than 100 server variations from shared parts 47.
Inside the GB200 NVL72, four vertical cartridges carry more than 5,000 copper cables for the GPU links 48. The power rises from here: NVIDIA is moving AI data centres to 800-volt DC power, which it says carries over 150% more power through the same copper, and its Vera Rubin compute tray is 100% liquid cooled with a circuit-board midplane replacing cables 49. Cooling maker Vertiv says air cooling reaches its limits as racks go past 20 kW and approach 50 kW 50, which is why the newest AI racks are liquid cooled.
The world sold $791.7 billion of chips in 2025, up 25.6% on 2024, according to the Semiconductor Industry Association 51. A handful of companies do the hardest steps: ASML makes all EUV machines 10; TSMC made chips for 534 customers in 2025 23; SK hynix, Samsung and Micron make the AI memory.
Governments are paying to move packaging closer to chip design. The US Commerce Department awarded Amkor up to $407 million for an advanced packaging and test plant in Peoria, Arizona 56; NIST describes its focus as 2.5D packaging, "the final step in the manufacturing of GPUs and other AI chips" 57. Amkor later raised the campus investment to $7 billion, with production starting in early 2028 58, and TSMC agreed that Amkor would offer its CoWoS and InFO packaging there 59. SK hynix received a $458 million award for an HBM packaging plant in West Lafayette, Indiana, with mass production planned for the second half of 2028 60. Until these open, every advanced packaging fab TSMC lists is in Taiwan 35.
60 sources, all checked September 2026. Official = the company or organisation’s own page; Filing = a document filed with a regulator or an annual report; Standard = a published industry standard; Paper = a peer-reviewed or conference paper; Research = an independent research body; Government = a government page; Press = news coverage, used only where no official source exists.
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