NVIDIA Rubin: The Complete Guide

A separate variant, Rubin CPX, was unveiled 9 September 2025 as a monolithic-die GPU built specifically for massive-context inference — long documents, video and code — distinct from the standard dual-die Rubin GPU described on this page 3.

First shown 18 March 2025 at GTC as a named future generation 1. A specialised variant, Rubin CPX, was detailed 9 September 2025 3. NVIDIA declared the Rubin platform in “full production” at CES on 5 January 2026, describing it as “six new chips” 2. GTC 2026 (16 March 2026) expanded this into the full Vera Rubin platform and named NVIDIA’s next architecture after Rubin as “Feynman” 4.

NVIDIA’s architecture deep-dive states Rubin uses “two dies … unified on a single package through a high-speed inter-die link called the NVIDIA High-Bandwidth Interface (NV-HBI)” 5 — not the monolithic design used for the separate Rubin CPX variant. NVIDIA states 336 billion transistors, 224 SMs and 896 fifth-generation Tensor cores 5. A third-generation Transformer Engine adds hardware-accelerated adaptive compression 2. NVIDIA has not published a process node or foundry for Rubin — no TSMC name, no node number appears in its architecture blog, newsroom or investor material found as of this check; this page does not infer one.

Figures per NVIDIA’s own Rubin architecture blog 5. A separate NVIDIA developer-blog roundup of the wider platform additionally lists a training-side NVFP4 figure; this page reports only the inference figure that NVIDIA’s dedicated architecture page states directly, since the training figure could not be pinned to one canonical source.

Unlike Blackwell and Blackwell Ultra, where NVIDIA names TSMC and a specific custom node (4N, 4NP) in its own architecture pages, no equivalent statement was found for Rubin in NVIDIA’s newsroom, developer blog or investor materials as of September 2026. Any specific foundry or node figure reported elsewhere is analyst inference, not an NVIDIA claim, and is not repeated here.

The rack-scale system built around Rubin — Vera Rubin NVL72, pairing 72 Rubin GPUs with 36 Vera CPUs — is covered on its own Vera Rubin page. System builders named for the platform include Dell Technologies, HPE, Lenovo, Supermicro and Cisco, alongside a long list of component and manufacturing partners 6.

No NVIDIA source, and no cloud provider’s own pricing page, publishes a Rubin price as of this check. Any dollar figures circulating for Rubin trace to analyst cost modelling, not NVIDIA or its partners, and are not reported on this page.

Platform-level performance claims are reported on the Vera Rubin page, since NVIDIA states most of its comparisons (inference token cost, training GPU count) at the platform level rather than for the Rubin GPU in isolation. As of September 2026, no MLPerf or other independent benchmark submission for Rubin has been published, because the platform has not yet shipped in volume.

NVIDIA’s Rubin platform newsroom page states the platform succeeds “the NVIDIA Blackwell platform” 2. At GTC 2026, NVIDIA named its next architecture generation Feynman, paired with a new CPU codenamed Rosa, continuing the pattern of naming data-center architectures after scientists 4. No official year has been stated for Feynman in NVIDIA’s own material found as of this check; any specific year attached to it elsewhere is press or analyst estimate, not an NVIDIA claim.

NVIDIA has named its data-center GPU architectures after scientists for years — Pascal, Volta, Turing, Ampere, Hopper, Blackwell — but Rubin marks the first one named for a woman 1. NVIDIA then continued the pattern with the next generation’s CPU, codenamed Rosa after Rosalind Franklin, confirmed at GTC 2026 4 — suggesting a deliberate choice rather than a one-off.