How to read this page. Each section starts Simple, then goes to a Deep dive: stop wherever you have what you need. The small numbers are sources: click one to open the original document. Where the maker has not published a figure -- a price, a die size, a factory address -- this page says so rather than estimate it.
1.At a glance
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MI455X is AMD’s newest AI chip, part of the MI400 series, in production from July 2026. It does not ship alone — AMD sells it inside Helios, a complete rack that pairs 72 MI455X chips with 18 of AMD’s own EPYC “Venice” CPUs 12.
Deep diveThe technical detail
MI455X was first previewed at AMD’s Advancing AI 2025 event on 12 June 2025 3, then entered production a little over a year later. AMD’s own July 2026 material treats the chip and the Helios rack as one story rather than two — nearly every performance figure AMD publishes for MI455X is stated at the rack level, not the single-chip level 4.
2.Launch and history
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Three of the largest names in AI — OpenAI, Meta and Anthropic — have each signed multi-gigawatt deals for chips from this exact family, alongside Oracle and Microsoft. AMD’s next few years of AI-chip revenue rest heavily on this one generation actually shipping on schedule.
Deep diveThe technical detail
All five deals are dated within a single 12-month stretch: Oracle (October 2025), OpenAI (October 2025), Meta (February 2026), Microsoft (July 2026) and Anthropic (July 2026) 56789 — see the Systems section for the figures behind each one. That concentration is itself worth noting: MI455X is not one customer’s chip, it is the chip AMD is betting several of its largest relationships on at once.
3.What’s inside it
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MI455X uses AMD’s fifth-generation CDNA architecture and carries 256 Work Group Processors, per AMD’s own product page 10.
Deep diveThe technical detail
AMD’s MI400 product page states the architecture directly as “5th Gen AMD CDNA architecture” with 256 Work Group Processors 10. AMD does not publish a transistor count or a specific manufacturing process node for the MI455X GPU die itself on this page or in any other official material this page could find — a figure of 320 billion transistors circulates in secondary technology coverage, but this page does not repeat it without an AMD source confirming it.
4.Full spec table
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432 GB of HBM4 memory, up to 23.3 TB/s of memory bandwidth, 40 PFLOPS of FP4 performance, 20 PFLOPS of FP8 10.
Deep diveThe technical detail
| Spec | AMD Instinct MI455X |
|---|
| Architecture | 5th Gen AMD CDNA |
|---|
| Work Group Processors | 256 |
|---|
| Memory | 432 GB HBM4, integrated |
|---|
| Memory bandwidth | up to 23.3 TB/s peak theoretical, per AMD’s current product page and Helios launch blog. AMD’s own June 2025 preview is reported by secondary outlets as showing a lower 19.6 TB/s figure at the time; this page could not confirm that earlier figure directly from AMD’s own June 2025 text, so only the current 23.3 TB/s figure is stated as fact |
|---|
| FP4 (dense) | 40 PFLOPS peak |
|---|
| FP8 (dense) | 20 PFLOPS peak |
|---|
| FP16 / BF16 | 5 PFLOPS peak |
|---|
| Process node | Not published by AMD for this GPU. AMD’s EPYC “Venice” CPU — the companion chip in the same Helios rack — is confirmed on TSMC’s 2-nanometre N2 process by a separate AMD release, but that release is explicitly about the CPU, not MI455X 11 |
|---|
| Transistors | Not published by AMD |
|---|
| TDP | Not published by AMD |
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Figures per AMD’s own MI400 product page 10. AMD does not say on this page whether the compute figures above are dense or include sparsity, unlike its MI350-series materials, which state this explicitly.
5.Where it’s made
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AMD has not published which foundry or process node makes the MI455X GPU itself. Its companion CPU in the same rack, EPYC “Venice”, is confirmed on TSMC’s 2-nanometre N2 process 11.
Deep diveThe technical detail
This is a genuine and specific gap in AMD’s own public material: AMD’s April 2025 press release states plainly that “Venice”, the CPU, is “the first HPC product in the industry to be taped out and brought up on the TSMC advanced 2nm (N2) process technology” 11 — but that claim is about the CPU by name, not the MI455X GPU that ships alongside it. Comments attributed to AMD’s CEO in earnings-call coverage suggest a 2-nanometre process for the MI450-series GPU too, but this page could not locate a primary AMD product page, press release or conference slide stating that directly for the GPU, so it reports the gap rather than repeating an unconfirmed figure.
6.Which systems use it
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MI455X ships inside Helios, a rack pairing 72 MI455X chips with 18 EPYC “Venice” CPUs, and is the chip behind AMD’s largest customer deals: OpenAI, Meta, Anthropic, Oracle and Microsoft 2.
Deep diveThe technical detail
| Customer | Announced | Terms |
|---|
| OpenAI | 6 Oct 2025 | 6 gigawatts of AMD GPUs over multiple generations, starting with 1 gigawatt of MI450-series chips in the second half of 2026; AMD issued OpenAI a warrant for up to 160 million AMD shares 612 |
| Meta | 24 Feb 2026 | 6 gigawatts of AMD Instinct GPUs, first gigawatt of custom MI450-series chips shipping in the second half of 2026; a matching 160-million-share warrant 7 |
| Oracle | 14 Oct 2025 | 50,000 MI450-series GPUs, initial deployment in the third quarter of 2026, expanding into 2027; Oracle named as first hyperscaler to offer a public AI supercluster on these chips 5 |
| Microsoft | 20 Jul 2026 | Deploying Helios (MI455X) on Azure, alongside 6th-generation EPYC “Venice”-based VM series, shipping from the second half of 2026 813 |
| Anthropic | 22 Jul 2026 | Up to 2 gigawatts of MI450-series chips in Helios racks, deployment beginning in the first half of 2027; AMD investing up to $5 billion in Anthropic as part of the deal 9 |
All five figures are AMD’s own stated terms, or a named counterparty’s own stated terms, dated within a single 12-month span (October 2025 to July 2026).
7.Official pricing
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Not published by AMD. MI455X is sold through Helios rack deployments and direct hyperscaler deals rather than listed with a per-chip or per-GPU-hour price.
Deep diveThe technical detail
Given that MI455X is brand new to production as of this page’s last check and its confirmed customers are hyperscalers buying at gigawatt scale rather than renting individual GPU-hours, no cloud provider’s own pricing page yet lists it, and AMD has not published a list price for the chip or the rack.
9.What came before, what came next
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Came before: the MI350 series, announced June 2025. What AMD says comes next: MI500 in 2027, MI600 in 2028.
Deep diveThe technical detail
AMD’s own July 2026 release states its roadmap in one line: “Next-generation AMD Instinct MI500 Series GPUs are coming in 2027, with next-generation compute, memory and interconnect technologies for leadership performance,” with MI600 series “coming in 2028” 2. AMD’s own June 2025 material had already described MI350-to-MI400 as up to a “4x generation-on-generation AI compute increase,” giving some sense of the pace AMD is claiming between generations 14.
10.Hidden in plain sight
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AMD barely talks about MI455X as a standalone chip — almost every number it publishes is at the level of the whole Helios rack, not the single GPU, which is itself a statement about how AMD expects this generation to be bought and used.
Deep diveThe technical detail
Helios’s own rack-level figures are striking on their own terms: 31 TB of combined HBM4 memory, 1.7 petabytes per second of combined bandwidth, 260 TB/s of scale-up networking bandwidth (AMD states this uses UALink, the open interconnect standard AMD co-founded, at 21.6 TB/s bidirectional per switch) and 43 TB/s of scale-out networking through AMD’s own Pensando “Vulcano” 800 Gbps network cards 154. At the rack level, AMD states 2.9 exaflops of dense FP4 compute and 1.4 exaflops of FP8 — figures that only make sense once you know they describe 72 chips working together, not one 4.