Huawei Ascend 910B / 910C: The Complete Guide

These two chips are covered on one page because they are the same generation on the same manufacturing process — the same pattern this site uses for same-generation chip families from other makers. 910B’s independent die analysis identifies a compute die codenamed “Virtuvian B”; 910C packages two of those dies together in a single multi-chip module 32. This page keeps the original Ascend 910 separate (its own page on this site) because independent analysis shows it was made on a different foundry entirely — see the “where it’s made” and “hidden in plain sight” sections below.

On 13 May 2025 the US Bureau of Industry and Security published guidance stating that certain integrated circuits, illustratively including “Huawei Ascend 910B / Huawei Ascend 910C / Huawei Ascend 910D,” are presumed subject to export restrictions under General Prohibition Ten 4. The original Ascend 910 (2019, TSMC-made) is not named in this guidance — only the 910B/910C/910D generation. A companion press release the same day announced the rescission of the prior administration’s AI Diffusion Rule and “strengthens chip-related export controls,” without naming specific models — the specific model names appear only in the linked guidance document, not the press release itself 5. Press coverage later reported that BIS removed language suggesting the restriction applied to any use “anywhere in the world,” a partial walk-back roughly a week after the original guidance 6 — this page states both the original guidance and that later softening, rather than only the stronger initial framing.

Tom’s Hardware’s die-teardown analysis counts 25 “New DaVinci” AI cores on the 910B compute die — fewer than the 32 cores on the original 910’s die, despite being the newer generation 3. Huawei has not published its own die diagram, transistor count, or core count for either chip — every architectural figure here beyond Huawei’s own system-level claims comes from this independent analysis, clearly labelled as such.

Die-level 910B figures per independent teardown analysis 3; 910C compute/memory figures per a secondary press compilation, not a direct Huawei-published datasheet — flagged here for verification rather than presented as confirmed 7. Huawei has not published a first-party spec sheet for either chip that this page could locate.

Tom’s Hardware’s analysis leaves the cause of the 910B’s larger die size and lower AI-core count, relative to the original TSMC-made 910, an open either/or: either SMIC’s process has “significantly lower transistor density” than TSMC’s N7+, or Huawei substantially changed the core design itself 3 — a press/analyst conclusion, not a Huawei statement, and not a settled verdict between the two explanations. This page states the SMIC attribution as third-party teardown analysis, not as something Huawei itself has confirmed, consistent with every foundry claim on this site’s Ascend pages.

Huawei’s own Huawei Connect 2025 keynote states more than 300 SuperPoD systems had been deployed, serving more than 20 customers, as of that keynote 9. The system uses Huawei’s own UnifiedBus interconnect to link the chips together — the system-level design, more than the individual chip, is where Huawei has published the most detail, consistent with this site’s wider finding that Huawei discloses more about its systems than about its individual chips.

Consistent with every Ascend chip on this site, Huawei does not publish chip prices. Analyst estimates of shipment volumes exist instead: SemiAnalysis’s own newsletter puts 2024 shipments at “507k Ascend units… the majority of which are 910Bs,” and 2025 shipments at “805k this year, 653k of those being 910C” 10 — a third-party volume estimate, not a price, and not independently verifiable against a Huawei-published figure. The same source calls these figures aspirational rather than guaranteed, noting China “can easily make more than 805k Huawei Ascends this year from TSMC and SMIC capacity, but they will not because they do not have enough HBM” — memory supply, not logic-chip manufacturing capacity, is the stated bottleneck 10.

Huawei’s own CloudMatrix 384 system, built from 384 Ascend 910C chips across 16 racks, is described in press coverage as delivering roughly 300 PFLOPS at BF16 against an NVIDIA GB200 NVL72 system’s roughly 180 PFLOPS — while drawing “nearly four times the power,” per the same press framing 2. This is a system-level comparison across two different chip counts and two different power budgets, not a per-chip benchmark, and this page presents it with that caveat rather than as a clean apples-to-apples result.

The jump from 910 to 910B is the clearest architectural break in the Ascend family this site has documented: a foundry switch, forced by export controls, visible directly in independent die measurements (see the Ascend 910 page). The jump from 910C to 950PR is a cleaner generational step — a new microarchitecture (SIMD+SIMT) and Huawei’s own first in-house HBM, rather than another forced foundry change 7.

The 13 May 2025 BIS guidance named “Huawei Ascend 910B, Huawei Ascend 910C” and a third chip, an “Ascend 910D,” as presumptively restricted 4 — notable because, per available reporting, the 910D had only reached the sampling/testing stage at that point, with this site finding no confirmed commercial launch for it as of September 2026. A chip was named in a US government export-restriction document before it had reached the market. Separately, press coverage reports that BIS removed the guidance’s original suggestion that using these chips “anywhere in the world” violated US export rules, about a week after first publishing it 6 — a real, sourced walk-back this page states directly rather than presenting the stronger initial framing as still-current policy.